Recently, with the advent of various next-generation smartphones, portable devices, and smart TVs, fusion processors integrating a multicore processor and a graphic accelerator have been developed to support various tangible 2D and 3D graphic processing.
Processors used in smartphones have evolved from a single core to dual-cores and anticipated to be advanced toward multi-cores of quad-cores or greater in the light of the development of processors and miniaturization trend of devices.
Also, a multicore processor integrating tens to hundreds of processors is expected to be applied to next-generation mobile terminals to implement biometrics and augmented reality.
Related art processors have performance improved by increasing a clock speed; however, an increase in speed leads to an increase in power consumption and generation of a larger amount of heat.
A multicore processor proposed to address the problem includes several cores, whereby individual cores may operate at a low frequency and power consumed by a single core may be distributed to several cores.
Installing a multicore processor equals installing two or more central processing units, and thus, an operation performed with a program supporting a multicore processor may be faster than that with a single core processor.
Also, when an operation is performed with the program supporting a multi-core processor, high performance can be secured in operations such as video compression and decompression, execution of games of high specification, implementation of augmented reality, and the like, in next-generation mobile terminals based on multimedia processing, compared to a single processor.
In order to develop an optimal multicore processor-based system on chip (SoC) structure, a design method at the level of a virtual platform-based system for initially analyzing functions and performance of SoC at a high level is required. A critical key factor in designing a virtual platform is designing an emulator that models a function of a multicore accurately.
Current multicore emulators support only emulation of a multicore processor operating with the same frequency on a chip in actuality and cannot provide a function of emulating a function of a multicore operating with different operating frequencies.
As illustrated in FIG. 1, related art processor core emulation schemes include an interpretive instruction set simulation (ISS) scheme as a scheme of emulation by modeling a pipeline of a processor core, a compile ISS scheme, and a dynamic code translation (DCT) scheme of emulation by translating a target code into a host machine code.
The interpretive ISS, a commercial ISS simulator, is ARMulator such as axd, rvdebuger, or the like, and the compile ISS is a scheme of emulating a processor core at a speed about 1000 times faster than interpretive ISS.
In order to develop a driver, firmware, and an application in a virtual platform emulator, a high speed emulation technique of a processor core with a speed of 10 to 100 MIPS is required.
In the related art, a processor core emulation scheme of performing host code execution directly in a host machine, rather than performing a target code based on DCT, is used.
FIG. 2 is a conceptual view illustrating a related art high speed emulation scheme based on DCT, in which a command is read from a binary image to search for a translation block (TB), and when the corresponding TB does not exist in a cache, a disassembling process is performed during which a function of an instruction is recognized and converted into a host machine (x86) command set.
The TB is stored in a TB cache. The TV may be executed as a function of a host machine as soon as it is stored.
When the same instruction is to be performed later, the already cached TB is retrieved from the TB cache, omitting a disassembling process consuming a great deal of time, and thus, an emulation speed may be increased by about 10 times, compared to a case in which the disassembling process is performed each time.
FIG. 3 is a conceptual view illustrating a multicore context switching scheme according to the related art. As illustrated in FIG. 3, an emulation scheme of four multicore processors based on DCT is realized with a multicore emulation manager that handles context switching between cores, and the multicore emulation manager emulates the four cores by performing context switching thereon in a sequential manner (Round-Robin manner).
In such a case, a workload allocation ratio of the cores (core 1 to core 4) is 1:1:1:1, and only emulation of multi-core processors operating with the same frequency is supported.
Namely, the related art multicore context switching scheme illustrated in FIG. 3 cannot emulate functions of multi-cores operating with different operating frequencies on a chip in actuality.